ASIC Verification Manager
Application
WHAT WE’RE UP TO
WE ARE A LEAN, TENACIOUS MACHINE POWERED BY 85 OF THE SHARPEST, MOST PASSIONATE PEOPLE WE COULD FIND.
Simelabs is a product-driven venture-development firm that works with a range of startups and big brands to create compelling, successful, award-winning application. We help people perfect and realise their visions for digital products. While others may just churn out what a client asks for, we strive to truly understand the problems our clients are aiming to solve and will stop at nothing to build solid products that we’re proud of.
Roles and Responsibilities
- Bachelor's degree in Electrical/Computer Engineering or Computer Science and 7+ years OR a Master's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience in Verification of ASIC, custom IC designs, and/or FPGA designBuild and lead the verification team.
- Drive the test bench architecture, verification plan and test bench development for full chip and subsystem verification.
- Mentor and lead a team of verification engineers to complete unit, subsystem and chip level verification.
- Develop and maintain methodology, flows, and sign-off criteria for verification.
The Ideal Candidate
- Experience with development of test bench architecture, test plan and test bench development for full chip and subsystem verification
- Hands on experience with System Verilog and VMM/OVM/UVM
- Hands-on experience with simulation tools including Synopsys VCS, Cadence IES to verify full-chip SoCs and FPGA based designs
- Requires strong understanding of state-of-the-art verification techniques, including assertion and metric-driven verification.
- Experience in AXI, DDR4, HBM, PCIe verification is a plus
- Verification experience in hardware accelerators and coprocessors is a plus
- Familiarity with verification management tools including regression management is required
- Familiarity with scripting in Python or Perl
- Strong understanding of ASIC and/or full custom chip development process is required
- Experience with FPGA programming and software is a plus
- Coherency and computer architecture experience is desirable
- Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques are a plus
Got what it takes?
Want to join the team? Submit your application—
we respond to most inquiries within three business days.
Perks and Benefits
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12 Paid Company Holidays
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6 Paid Sick Leave
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Group Health Plan insurance Employee, Spouse and dependent
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Performance Bonus
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Flexible time
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Work Life Balance